The present invention relates to integrated circuits and in particular to an electronic description of an integrated circuit that is encrypted to prevent the details of the circuit from being revealed while still allowing simulation of the integrated circuit, for example, for logic and fault simulation.
Complex integrated circuits, such as “system on chip” (SOC) designs can be constructed from circuit “building blocks” developed by different companies. The building blocks are assembled by combining electronic files describing each building block to produce the necessary integrated circuit masks needed to produce the ultimate integrated circuit.
These building blocks are often referred to as intellectual property (IP) cores, reflecting the fact that it is the underlying design (the intellectual property) that is sold by the designer as opposed to an actual integrated circuit. The ability to license IP cores provides substantial efficiency in the design of complex circuit elements by allowing the costs of developing an IP core to be shared among multiple manufacturers.
The abstract IP core is captured in an electronically readable circuit-level schematic describing each component, for example logic gates, and their interconnection, together with a functional description of the inputs and outputs to the IP core (the functional specification). While the sale of an IP core may include this entire functional specification (a so-called “soft” core), it is also possible to sell an electronic description of an IP core that provides only layout information and the functional description of the inputs and outputs without the circuit level schematic. This so-called “hard” core allows fabrication of the IP core but does not reveal information about the internal circuit configuration or components, preventing ready copying or modification of the IP core.
Normally a hard-core license for an IP core will be cheaper than a soft-core license because the hard-core license, by hiding the circuit design, reduces the risk that the purchaser will be able to compete with or develop commercial alternatives to the IP core or that the intellectual property of the IP core will be revealed. Nevertheless, the less-expensive hard-core license has significant drawbacks. Because the details of the underlying circuit are hidden, it is not possible to simulate the IP core alone or in combination with the other building block circuits. The ability to simulate operation of the IP core allows better integration with other circuit elements, for example, by revealing operating limitations such as signal propagation delays that need to be accommodated. Simulation is also important to identify how component faults will affect the IP core. Such fault simulation allows the end user to construct more efficient “built-in self test” (BIST) logic that can be used to test the operation of the IP core during manufacture. Generally, BIST logic identifies bit patterns or vectors that are used to detect faults in a logic circuit.
The practical ability to select only between a hard-core or soft-core licensing model substantially limits the market for IP cores in many important applications where IP core simulation is required, but purchasing a soft-core license is too costly